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rt9618/a 1 ds9618/a-06 april 2011 www.richtek.com features z z z z z drives two n-mosfets z z z z z adaptive shoot-through protection z z z z z embedded boot strapped diode z z z z z support high switching frequency z z z z z fast output rise time z z z z z small sop-8 and 8-lead wdfn package z z z z z tri-state input for bridge shutdown z z z z z supply under voltage protection z z z z z upper mosfet direct shorted protection z z z z z rohs compliant and 100% lead (pb)-free applications z core voltage supplies for desktop, motherboard cpu z high frequency low profile dc-dc converters z high current low voltage dc-dc converters synchronous-rectified buck mosfet drivers general description the rt9618/a are high frequency, dual mosfet drivers specifically designed to drive two power n-mosfets in a synchronous-rectified buck converter topology. the drivers combined with richtek ? s series of multi-phase buck pwm controller form a complete core-voltage regulator solution for advanced micro-processors. the rt9618/a drive both the lower/upper gate in a synchronous-rectifier bridge with 12v. this drive-voltage flexibility provides the advantage of optimizing applications involving trade-offs between switching losses and conduction losses. rt9618a has longer ugate/lgate deadtime which can drive the mosfets with large gate rc value, avoiding the shoot-through phenomenon. rt9618 is targeted to drive low gate rc mosfets and performs better efficiency. the output drivers in the rt9618/a can efficiently switch power mosfets at frequency up to 500khz. switching frequency above 500khz has to take into account the thermal dissipation of the packages. rt9618/a are capable to drive a 3nf load with a 30ns rise time. rt9618/a implements bootstrapping on the upper gate with an external capacitor and an embedded diode. this reduces implementation complexity and allows the use of higher performance, cost effective n-mosfets. adaptive shoot- through protection is integrated to prevent both mosfets from conducting simultaneously. pin configurations (top view) sop-8 ordering information 2 3 4 5 8 7 6 boot vcc od pwm ugate lgate pgnd phase note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. wdfn-8l 3x3 marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. boot vcc pwm od 7 6 5 1 2 3 4 8 gnd 9 ugate lgate pgnd phase rt9618/a package type s : sop-8 qw : wdfn-8l 3x3 lead plating system p : pb free g : green (halogen free and pb free) long dead time short dead time
rt9618/a 2 ds9618/a-06 april 2011 www.richtek.com functional pin description pin no. rt9618/a s r t9618/a qw pin name pin function 1 1 boot floating bootstrap supply pin for upper gate drive. 2 2 pwm input pwm signal for controlling the driver. 3 3 od output disable. when low, both ugate and lgate are driven low and the normal operation is disabled. 4 4 vcc +12v supply voltage. 5 5 lgate lower gate drive output. connected to gate of low-side power n-mosfet. 6 6 pgnd common ground. 7 7 phase connected this pin to the source of the high-side mosfet and the drain of the low-side mosfet. 8 8 ugate upper gate drive output. connected to gate of high-side power n-mosfet. -- 9 (exposed pad) gnd the exposed pad must be soldered to a large pc b and connected to gn d for maximum power dissipation. typical application circuit vcc pwm pgnd boot ugate phase lgate rt9618/a 1uf 2.2 q1 atx_12v 1uf pwm d1 3.3nf 1uh + 2200uf + 2200uf + 10uf + 10uf 1 10 2.2uh 1000uf 1000uf 10uf 10uf 1000uf 10uf 10uf atx_12v v core q2 2.2 0 1 2 8 5 7 6 4 3 od c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 r1 r2 r3 r4 r5 l1 l2 v in +5v
rt9618/a 3 ds9618/a-06 april 2011 www.richtek.com function block diagram timing diagram pwm ugate lgate t pdhugate t pdllgate t pdlugate t pdhlgate 90% 90% 2v 2v 2v 2v shoot-through protection turn off detect shoot-through protection input disable vcc pwm internal 5v boot ugate phase lgate pgnd r r vcc por od
rt9618/a 4 ds9618/a-06 april 2011 www.richtek.com electrical characteristics recommended operating conditions (note 4) z supply voltage, v cc ------------------------------------------------------------------------------------- 12v 10% z junction temperature range --------------------------------------------------------------------------- 0 c to 125 c z ambient temperature range --------------------------------------------------------------------------- 0 c to 70 c parameter symbol test conditions min typ max units v cc supply voltage power supply voltage v cc 7.3 -- 13.5 v v cc supply current power supply current i vcc v boot = 12v, pwm = 0v -- 1 2.5 ma power-on reset por threshold v vccrth v cc rising 5.5 6.4 7.3 v to be continued (recommended operating conditions, t a = 25 c unless otherwise specified) absolute maximum ratings (note 1) z supply voltage, v cc ------------------------------------------------------------------------------------- ? 0.3v to 15v z boot to phase ----------------------------------------------------------------------------------------- ? 0.3v to 15v z boot to gnd dc ------------------------------------------------------------------------------------------------------------ ? 0.3v to v cc + 15v < 200ns ----------------------------------------------------------------------------------------------------- ? 0.3v to 42v z phase to gnd dc ------------------------------------------------------------------------------------------------------------ ? 5v to 15v < 200ns ----------------------------------------------------------------------------------------------------- ? 10v to 30v z lgate dc ------------------------------------------------------------------------------------------------------------ gnd ? 0.3v to v cc + 0.3v < 200ns ----------------------------------------------------------------------------------------------------- ? 2v to v cc + 0.3v z ugate ------------------------------------------------------------------------------------------------------ v phase ? 0.3v to v boot + 0.3v < 200ns ----------------------------------------------------------------------------------------------------- v phase ? 2v to v boot + 0.3v z pwm input v oltage -------------------------------------------------------------------------------------- gnd ? 0.3v to 7v z od ------------------------------------------------------------------------------------------------------------ gnd ? 0.3v to 7v z power dissipation, p d @ t a = 25 c sop-8 ------------------------------------------------------------------------------------------------------- 0.625w wdfn-8l 3x3 --------------------------------------------------------------------------------------------- 0.909w z package thermal resistance (note 2) sop-8, ja ------------------------------------------------------------------------------------------------- 160 c/w wdfn-8l 3x3, ja ---------------------------------------------------------------------------------------- 110 c/w wdfn-8l 3x3, jc --------------------------------------------------------------------------------------- 8.2 c/w z lead temperature (soldering, 10 sec.) -------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------- ? 40 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------- 200v
rt9618/a 5 ds9618/a-06 april 2011 www.richtek.com parameter symbol test conditions min typ max units hysteresis v vcchys -- 2.2 -- v pwm input maximum input current i pwm pwm = 0v or 5v -- 300 -- a pwm floating voltage v pwmfl v cc = 12v -- 2.4 -- v pwm rising threshold v pwmrth 3.2 3.6 3.9 v pwm falling t hreshold v pwmfth 1.1 1.3 1.5 v output disable input od rising threshold v odrth 1.5 1.8 2.1 v od hysteresis v odhys -- 0.5 -- v timing ugate rise time t rugate v cc = 12v, 3nf load -- 27 35 ns ugate fall time t fugate v cc = 12v, 3nf load -- 32 45 ns lgate rise time t rlgate v cc = 12v, 3nf load -- 35 45 ns lgate fall time t flgate v cc = 12v, 3nf load -- 27 38 ns rt9618 -- 20 -- rt9618a t pdhugate -- 90 -- t pdlugate v boot ? v phase = 12v see timing diagram -- 15 -- t pdhlgate -- 20 -- propagation delay rt9618/a t pdllgate see timing diagram -- 8 -- ns output ugate drive source r ugatesr v boot ? v phase = 12v -- 1.9 3 ugate drive sink r ugatesk v boot ? v phase = 12v -- 1.4 3 lgate drive source r lgatesr v cc = 12v -- 1.9 3 lgate drive sink r lgatesk v cc = 12v -- 1.1 2.2 note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. the case point of jc is on the expose pad for the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
rt9618/a 6 ds9618/a-06 april 2011 www.richtek.com typical operating characteristics time (25ns/div) pwm to drive waveform phase (10v/div) ugate (20v/div) pwm (5v/div) lgate (10v/div) no load time (25ns/div) pwm to drive waveform phase (10v/div) ugate (20v/div) pwm (5v/div) lgate (10v/div) no load dead time time (20ns/div) 30a/ch phase lgate ugate (5v/div) dead time time (20ns/div) 30a/ch phase lgate ugate (5v/div) high side mosfet : fr3707z x 1, low side mosfet : lr8113 x 2 time (1 s/div) drive enable phase (10v/div) ugate (20v/div) lgate (10v/div) no load od (2v/div) phase (10v/div) ugate (20v/div) lgate (10v/div) drive disable time (1 s/div) no load od (2v/div)
rt9618/a 7 ds9618/a-06 april 2011 www.richtek.com dead time time (20ns/div) no load phase lgate ugate (5v/div) dead time time (20ns/div) no load phase lgate ugate (5v/div) (5v/div) short pulse time (20ns/div) i out = 119a to 24a phase lgate ugate internal diode i-v curve 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 voltage (v) current (a)
rt9618/a 8 ds9618/a-06 april 2011 www.richtek.com application information the rt9618/a are designed to drive both high side and low side n-mosfet through externally input pwm control signal. it has power-on protection function which held ugate and lgate low before vcc up across the rising threshold voltage. after the initialization, the pwm signal takes the control. the rising pwm signal first forces the lgate signal turns low then ugate signal is allowed to go high just after a non-overlapping time to avoid shoot- through current. the falling of pwm signal first forces ugate to go low. when ugate and phase signal reach a predetermined low level, lgate signal is allowed to turn high. the pwm signal is acted as "high" if above the rising threshold and acted as "low" if below the falling threshold. any signal level enters and remains within the shutdown window is considered as "tri-state", the output drivers are disabled and both mosfet gates are pulled and held low. if left the pwm signal floating, the pin will be kept around 2.4v by the internal divider and provide the pwm controller with a recognizable level. od pin will also shutdown the bridge of tied to gnd. the rt9618/a typically operate at frequency of 200khz to 500khz. it shall be noted that to place a 1n4148 or schottky diode between the vcc and boot pin as shown in the typical application circuit for ligher efficiency. non-overlap control to prevent the overlap of the gate drives during the ugate turn low and the lgate turn high, the non-overlap circuit monitors the voltages at the phase node and high side gate drive (ugate-phase). when the pwm input signal goes low, ugate begins to turn low (after propagation delay). before lgate can turn high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.2v. once the monitored voltages fall below 1.2v, lgate begins to turn high. for short pulse condtion, if the phase pin had not gone high after lgate turns low, the lgate has to wait for 200ns before turn high. by waiting for the voltages of the phase pin and high side gate drive to fall below 1.2v, the non-overlap protection circuit ensures that ugate is low before lgate turns high. in figure 1, the current i g1 and i g2 are required to move the gate up to 12v. the operation consists of charging c gd and c gs . c gs1 and c gs2 are the capacitances from gate to source of the high side and the low side power mosfets, respectively. in general data sheets, the c gs is referred as "c iss " w hich is the input capacitance. c gd1 and c gd2 are the capacitances from gate to drain of the high side and figure 1. equivalent circuit and associated waveforms 12v t t v g2 v g1 v phase +12v also to prevent the overlap of the gate drives during lgate turn low and ugate turn high, the non-overlap circuit monitors the lgate voltage. when lgate go below 1.2v, ugate is allowed to go high. driving power mosfets the dc input impedance of the power mosfet is extremely high. when v gs at 12v (or 5v), the gate draws the current only few nano-amperes. thus once the gate has been driven up to "on" level, the current could be negligible. however, the capacitance at the gate to source terminal should be considered. it requires relatively large currents to drive the gate up and down 12v (or 5v) rapidly. it also required to switch drain current on and off with the required speed. the required gate drive currents are calculated as follows. l s 2 c gs1 c gd1 i gd1 i gs1 i g1 v out s 1 v in d 1 d 1 gnd g 1 d 2 c gs2 g 2 i g2 i gd2 i gs2 c gd2 d 2
rt9618/a 9 ds9618/a-06 april 2011 www.richtek.com the total current required from the gate driving source is by a similar calculation, we can also get the sink current required from the turned off mosfet. select the bootstrap capacitor figure 2 sho ws part of the bootstrap circuit of rt9618/a. the v cb (the voltage difference between boot and phase on rt9618/a) provides a voltage to the gate of the high side power mosfet. this supply needs to be ensured that the mosfet can be driven. for this, the capacitance c b has to be selected properly. it is determined by following constraints. before driving the gate of the high side mosfet up to 12v (or 5v), the low side mosfet has to be off; and the high side mosfet is turned off before the low side is turned on. from figure 1, the body diode "d 2 " had been turned on before high side mosfets turned on. before the low side mosfet is turned on, the c gd2 have been charged to v in . thus, as c gd2 reverses its polarity and g 2 is charged up to 12v, the required current is it is helpful to calculate these currents in a typical case. assume a synchronous rectified buck converter, input voltage v in = 12v, v g1 = v g2 = 12v. the high side mosfet is phb83n03lt whose c iss = 1660pf, c rss = 380pf, and t r = 14ns. the low side mosfet is phb95n03lt whose c iss = 2200pf, c rss = 500pf and t r = 30ns, from the equation (1) and (2) we can obtain from equation. (3) and (4) gd1 gd1 gd1 r1 dv 12v ic c dt t == (3) (4) r2 gd2 gd2 gd2 t 12v vi c dt dv c i + = = (a) 0.88 10 30 12 10 2200 i (a) 1.428 10 14 12 10 1660 i 9 - 12 - 9 - -12 gs2 gs1 = = = = (5) (6) (7) (8) (9) (10) r2 gs1 gs1 gs2 r1 gs1 gs1 gs1 t 12 c dt dvg2 c i t 12 c dt dvg1 c i = = = = (1) (2) the low side power mosfets, respectively and referred to the data sheets as "c rss " the reverse transfer capacitance. for example, t r1 and t r2 are the rising time of the high side and the low side power mosfets respectively, the required current i gs1 and i gs2 , are showed below : (a) 0.4 10 30 12) (12 10 500 i (a) 0.326 10 14 12 10 380 i 9 - 12 - 9 - -12 gd2 gd1 = + = = = (a) 1.28 0.4) (0.88 i i i (a) 1.754 0.326) (1.428 i i i gd2 gs2 g2 gd1 gs1 g1 = + = + = = + = + = v in c b v cb + - boot v cc v cc ugate phase lgate pgnd 1n4148 figure 2. part of bootstrap circuit of rt9618/a in practice, a low value capacitor c b will lead the over- charging that could damage the ic. therefore to minimize the risk of overcharging and reducing the ripple on v cb , the bootstrap capacitor should not be smaller than 0.1 f, and the larger the better. in general design, using 1uf can provide better performance. at least one low-esr capacitor should be used to provide good local de-coupling. here, to adopt either a ceramic or tantalum capacitor is suitable. power dissipation for not exceeding the maximum allowable power dissipation to drive the ic beyond the maximum recommended operating junction temperature of 125 c, it is necessary to calculate power dissipation appro-priately.
rt9618/a 10 ds9618/a-06 april 2011 www.richtek.com the operating junction temperature can be calculated from the power dissipation curves (figure 4). assume v cc =12v, operating frequency is 200khz and the c u =c l =1nf which emulate the input capacitances of the high side and low side power mosfets. from figure 4, the power dissipation is 100mw. for rt9618/a, the sop-8 package thermal resistance ja is 160 c/w, the operating junction temperature is calculated as : 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 frequency (khz) power dissipation (mw) c u =c l =3nf c u =c l =1nf c u =c l =2nf power dissipation vs. frequency layout consideration figure 5 show s the schematic circuit of a two-phase synchronous buck converter to implement the rt9618/a. the converter operates from 5v to 12v of v in . when layout the pcb, it should be very careful. the power- circuit section is the most critical one. if not configured properly, it will generate a large amount of emi. the junction of q1, q2, l2 should be very close. next, the trace from ugate, and lgate should also be short to decrease the noise of the driver output signals. phase signals from the junction of the power mosfet, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. the bypass capacitor c4 should be connected to pgnd directly. furthermore, the bootstrap capacitors (c b ) should always be placed as close to the pins of the ic as possible. figure 3. test circuit this dissipation is a function of switching frequency and total gate charge of the selected mosf et. figure 3 shows the power dissipation test circuit. c l and c u are the ugate and lgate load capacitors, respectively. the bootstrap capacitor value is 0.01uf. figure 4 shows the power dissipation of the rt9618/a as a function of frequency and load capacitance. the value of the c u and c l are the same and the frequency is varied from 100khz to 1mhz. figure 4. power dissipation vs. frequency t j = (160 c/w x 100mw) + 25 c = 41 c (11) where the ambient temperature is 25 c. the method to improve the thermal transfer is to increase the pcb copper area around the rt9618/a first. then, adding a ground pad under ic to transfer the heat to the peripheral of the board. vcc pwm pgnd boot ugate phase lgate rt9618/a 1uf c l 3nf 20 c u 3nf 2n7002 2n7002 +12v +12v 1uf pwm 1n4148 c boot 10 5v od boot ugate phase lgate vcc rt9618/a 1 4 5 7 8 pgnd 6 d1 1uf c b 1.2uh 12v 1500uf l1 c3 v in v core 1uf c2 phb83n03lt phb95n03lt 2uh l2 q2 q1 1000uf c1 + + 12v pwm 2 pwm 3 5v od 1uf c4 10 r1 figure 5. two-ph ase synchronous buck converter circuit
rt9618/a 11 ds9618/a-06 april 2011 www.richtek.com outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050
rt9618/a 12 ds9618/a-06 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringemen t of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed b y richtek. dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.200 2.700 0.087 0.106 e 2.950 3.050 0.116 0.120 e2 1.450 1.750 0.057 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 8l dfn 3x3 package, 0.5mm lead pitch 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a

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